Fujitsu FR81S User Manual

CHAPTER 8: DMA CONTROLLER (DMAC)

5. Operation

FUJITSU SEMICONDUCTOR LIMITED

CHAPTER : DMA CONTROLLER (DMAC)

FUJITSU SEMICONDUCTOR CONFIDENTIAL

Table 5-2 Relationship between Transfer Request Detection Conditions and Transfer Mode

Block transfer

Burst transfer

Request by software

Set the DCCRn:CE bit to "1".

Set the DCCRn:CE bit to

"1".

Request by interrupt

Edge detection

Also, the relationship between the detected transfer request and the DMACR:DME and DCCRn:CE bits is

given on Table 5-3. If the DME bit or CE bit is cleared during transfer, the block transfer is stopped.

Table 5-3 Relationship between Transfer Requests and DME/CE Bits

DME bit

CE bit

DME/CE clear

The already detected transfer request is

not cleared.

The already detected transfer

request is cleared.

DME/CE

setting after

the transfer

interrupt

Block transfer

When a new transfer request is detected,

the data transfer is restarted based on the

priority.

When a new transfer request is

detected, the data transfer is

restarted based on the priority.

Burst transfer

When the DME bit is set, the data transfer

is restarted immediately based on the

priority.



Standby recovery request by DMA transfer request

If the MCU receives a transfer request in the standby mode, the DMAC requests the MCU to recover from

the standby mode. If data transfer is enabled and if a transfer request is asserted by the transfer request

source, a standby recovery is requested.



Channel priority

If multiple transfer requests are issued, the DMAC starts data transfer on the channel having the highest

priority. The channel priority can be fixed or can be set by round robin. The priority is determined for each

block transfer or when data transfer ends.

•

Fixed priority (DMACR:AT = 0)

The channel priority is fixed in the sequence of "ch.0 > ch.1 > ch.2 > ch.3". The following gives an

example.

Example 1 : If transfer requests are issued on ch.0, ch.1 and ch.3 simultaneously, data transfer starts from

ch. 0. When data transfer ends on ch.0, the next data transfer starts on ch.1. After data

transfer on ch.1, the next data transfer starts on ch.3. The following gives transfer examples.

Dotted lines in the figure show the block delimiters.

Transfer request : Requests are issued for ch0, ch.1 and ch.3 simultaneously.

Setting

: Ch.0, ch.1 and ch.3 are set to the burst transfer mode, and data transfer occurs 3 times.

MB91520 Series

MN705-00010-1v0-E

335