Fujitsu FR81S User Manual

CHAPTER 8: DMA CONTROLLER (DMAC)

5. Operation

FUJITSU SEMICONDUCTOR LIMITED

CHAPTER : DMA CONTROLLER (DMAC)

FUJITSU SEMICONDUCTOR CONFIDENTIAL



Reloading of transfer count

If the reloading of the transfer count has been set, the DTCRn:DTC bit is returned to the initial value after

the data transfer.

If reloading of the transfer count is disabled, the DTCRn:DTC bit is set to "0" after the data transfer.

If the specified number of times of transfer is suspended or abnormally terminated, the DTCRn:DTC bit

indicates the remaining transfer count regardless of the reload setting of the transfer count.

Figure 5-9 Reloading of Transfer Count Register

The DCCRn:CE bit status varies after the data transfer, depending on the reload setting of the transfer count.

The following explains the relation between the transfer count reload setting and the transfer request source.

Table 5-5 DCCRn:CE Bit at the End of Transfer

Software request

Non-software request

If the reloading of transfer

count is set

The DCCRn:CE bit is cleared

The DCCRn:CE bit is not cleared

If the reloading of transfer

count is disabled

The DCCRn:CE bit is cleared



Transfer suspension

The DMAC suspends the DMA transfer due to the following causes.

⋅

A suspension as the DMACR:DME bit is cleared

⋅

A suspension as the DCCRn:CE bit is cleared

⋅

A suspension caused by the transfer stop request by the transfer request source peripheral

Data transfer is suspended in units of blocks. If data transfer is suspended, the next transfer is not started.

Data transfer is stopped. The settings to restart data transfer vary depending on the suspension cause.

⋅

A suspension as the DMACR:DME bit is cleared

If the DMACR:DME bit is cleared, all channels are stopped from operating. After a block of data has

been transferred on the current channel, the data transfer is suspended. To restart data transfer, set the

DMACR:DME bit.

⋅

A suspension as the DCCRn:CE bit is cleared

If the DCCRn:CE bit is cleared, the channel is stopped from operating. After a block of data has been

transferred, the data transfer is suspended. Also, as the DCCRn:CE bit is cleared, the already detected

transfer request is cleared. To restart data transfer, set the DCCRn:CE bit for the stopped channel and

issue a new transfer request.

⋅

A transfer stop request from the transfer request source peripheral

The following peripherals can issue a transfer stop request under certain conditions.

(register write)

Transfer count register

Transfer count

reload register

Reload after the transfer

Update register (-1)

MB91520 Series

MN705-00010-1v0-E

340