Fujitsu FR81S User Manual
CHAPTER 9: GENERATION AND CLEARING OF DMA
TRANSFER REQUESTS
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER
: GENERATION AND CLEARING OF DMA TRANSFER REQUESTS
FUJITSU SEMICONDUCTOR CONFIDENTIAL
15
4.6. DMA Request Clear Register 6 : ICSEL6 (Interrupt
Clear SELect register 6)
The bit configuration of DMA request clear register 6 is shown below.
These bits are used to select the peripheral that has generated the interrupt to be cleared (assigned to
interrupt vector number #40).
ICSEL6: Address 0406
H
(Access : Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Reserved
PPGSEL0[3:0]
Initial value
0
0
0
0
0
0
0
0
Attribute R0,WX
R0,WX
R0,WX
R0,WX
R/W
R/W
R/W
R/W
[bit3 to bit0] PPGSEL0[3:0] (PPG SELection0) : Interrupt clear selection bits for PPG0, 1, 10, 11, 20,
21
PPGSEL0[3:0]
Clear target
0000
PPG0
0001
PPG1
0010
PPG10
0011
PPG11
0100
PPG20
0101
PPG21
0110
Reserved (Does not clear any)
0111
Reserved (Does not clear any)
1000
16-bit free-run timer 1 zero detection
1001
16-bit free-run timer 1 compare clear
1010 to 1111
Reserved (Does not clear any)
Note:
Setting PPGSEL0[3:0]= "0110", "0111" and "1010" to "1111" are prohibited. During this setting, no
interrupt clear will be selected.
MB91520 Series
MN705-00010-1v0-E
360