Fujitsu FR81S User Manual
CHAPTER 9: GENERATION AND CLEARING OF DMA
TRANSFER REQUESTS
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER
: GENERATION AND CLEARING OF DMA TRANSFER REQUESTS
FUJITSU SEMICONDUCTOR CONFIDENTIAL
16
4.7. DMA Request Clear Register 7 : ICSEL7 (Interrupt
Clear SELect register 7)
The bit configuration of DMA request clear register 7 is shown below.
These bits are used to select the peripheral that has generated the interrupt to be cleared (assigned to
interrupt vector number #41).
ICSEL7: Address 0407
H
(Access: Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Reserved
PPGSEL1[3:0]
Initial value
0
0
0
0
0
0
0
0
Attribute R0,WX
R0,WX
R0,WX
R0,WX
R/W
R/W
R/W
R/W
[bit3 to bit0] PPGSEL1[3:0] (PPG SELection1) : Interrupt clear selection bits for PPG2, 3, 12, 13, 22,
23
PPGSEL1[3:0]
Clear target
0000
PPG2
0001
PPG3
0010
PPG12
0011
PPG13
0100
PPG22
0101
PPG23
0110
Reserved (Does not clear any)
0111
Reserved (Does not clear any)
1000
16-bit free-run timer 2 zero detection
1001
16-bit free-run timer 2 compare clear
1010 to 1111
Reserved (Does not clear any)
Note:
Setting PPGSEL1[3:0]= "0110", "0111" and "1011" to "1111" are prohibited. During this setting, no
interrupt clear will be selected.
MB91520 Series
MN705-00010-1v0-E
361