Fujitsu FR81S User Manual
CHAPTER 9: GENERATION AND CLEARING OF DMA
TRANSFER REQUESTS
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER
: GENERATION AND CLEARING OF DMA TRANSFER REQUESTS
FUJITSU SEMICONDUCTOR CONFIDENTIAL
19
4.10. DMA Request Clear Register 10 : ICSEL10 (Interrupt
Clear SELect register 10)
The bit configuration of DMA request clear register 10 is shown below.
These bits are used to select the peripheral that has generated the interrupt to be cleared (assigned to
interrupt vector number #44).
ICSEL10: Address 040A
H
(Access : Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Reserved
PPGSEL4[1:0]
Initial value
0
0
0
0
0
0
0
0
Attribute R0,WX R0,WX R0,WX R0,WX R0,WX R0,WX
R/W
R/W
[bit1, bit0] PPGSEL4[1:0] (PPG SELection4) : Interrupt clear selection bits for PPG8, 9, 18, 19
PPGSEL4[1:0]
Clear target
00
PPG8
01
PPG9
10
PPG18
11
PPG19
MB91520 Series
MN705-00010-1v0-E
364