Fujitsu FR81S User Manual
CHAPTER 9: GENERATION AND CLEARING OF DMA
TRANSFER REQUESTS
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER
: GENERATION AND CLEARING OF DMA TRANSFER REQUESTS
FUJITSU SEMICONDUCTOR CONFIDENTIAL
20
4.11. DMA Request Clear Register 11 : ICSEL11 (Interrupt
Clear SELect register 11)
The bit configuration of DMA request clear register 11 is shown below.
These bits are used to select the peripheral that has generated the interrupt to be cleared (assigned to
interrupt vector number #46).
ICSEL11: Address 040B
H
(Access : Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Reserved
PMSTSEL[2:0]
Initial value
0
0
0
0
0
0
0
0
Attribute R0,WX
R0,WX
R0,WX
R0,WX
R0,WX
R/W
R/W
R/W
[bit2 to bit0] PMSTSEL[2:0] (PLL, Main, Sub Timer SELection) : Interrupt clear selection for main
timer / sub timer / PLL timer
PMSTSEL[2:0]
Clear target
000
Main timer
001
Sub timer
010
PLL timer
011
Multi-function serial ch.8 transmission completion
100
16-bit ICU2
101
16-bit ICU3
110
Reserved (Does not clear any)
111
Reserved (Does not clear any)
Note:
Setting PMSTSEL[2:0]= "110" and "111" are prohibited. During this setting, no interrupt clear will be
selected.
MB91520 Series
MN705-00010-1v0-E
365