Fujitsu FR81S User Manual
CHAPTER 9: GENERATION AND CLEARING OF DMA
TRANSFER REQUESTS
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER
: GENERATION AND CLEARING OF DMA TRANSFER REQUESTS
FUJITSU SEMICONDUCTOR CONFIDENTIAL
26
4.17. DMA Request Clear Register 18 : ICSEL18 (Interrupt
Clear SELect register 18)
The bit configuration of DMA request clear register 18 is shown below.
These bits are used to select the peripheral that has generated the interrupt to be cleared (assigned to
interrupt vector number #57).
ICSEL18: Address 0412
H
(Access : Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Reserved
ICUSEL5[4:0]
Initial value
0
0
0
0
0
0
0
0
Attribute R0,WX
R0,WX
R0,WX
R/W
R/W
R/W
R/W
R/W
[bit4 to bit0] ICUSEL5[4:0] : Interrupt clear selection for ICU ch.5
ICUSEL5[4:0]
Clear target
00000
32-bit ICU ch.5
00001
Reserved (Does not clear any)
00010
A/D converter ch.32
00011
A/D converter ch.33
00100
A/D converter ch.34
00101
A/D converter ch.35
00110
A/D converter ch.36
00111
A/D converter ch.37
01000
A/D converter ch.38
01001
A/D converter ch.39
01010
A/D converter ch.40
01011
A/D converter ch.41
01100
A/D converter ch.42
01101
A/D converter ch.43
01110
A/D converter ch.44
01111
A/D converter ch.45
10000
A/D converter ch.46
10001
A/D converter ch.47
10010 to 11111
Reserved (Does not clear any)
Note:
Setting ICUSEL5[4:0]= "00001" and "10010" to "11111" are prohibited. During this setting, no interrupt
clear will be selected.
MB91520 Series
MN705-00010-1v0-E
371