Fujitsu FR81S User Manual
CHAPTER 9: GENERATION AND CLEARING OF DMA
TRANSFER REQUESTS
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER
: GENERATION AND CLEARING OF DMA TRANSFER REQUESTS
FUJITSU SEMICONDUCTOR CONFIDENTIAL
28
4.19. DMA Request Clear Register 20 : ICSEL20 (Interrupt
Clear SELect register 20)
The bit configuration of DMA request clear register 20 is shown below.
These bits are used to select the peripheral that has generated the interrupt to be cleared (assigned to
interrupt vector number #59).
ICSEL20: Address 0414
H
(Access : Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Reserved
OCUSEL1[2:0]
Initial value
0
0
0
0
0
0
0
0
Attribute R0,WX R0,WX R0,WX R0,WX R0,WX
R/W
R/W
R/W
[bit2 to bit0] OCUSEL1[2:0] (OCU Selection1) : Interrupt clear selection bits for OCU8, 9
OCUSEL1[2:0]
Clear target
000
Reserved (Does not clear any)
001
Reserved (Does not clear any)
010
Reserved (Does not clear any)
011
Reserved (Does not clear any)
100
32-bit OCU8
101
32-bit OCU9
110
Reserved (Does not clear any)
111
Reserved (Does not clear any)
Note:
Setting OCUSEL1[2:0]= "000" to "011" and "110" to "111" are prohibited. During this setting, no interrupt
clear will be selected.
MB91520 Series
MN705-00010-1v0-E
373