Fujitsu FR81S User Manual
CHAPTER 9: GENERATION AND CLEARING OF DMA
TRANSFER REQUESTS
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER
: GENERATION AND CLEARING OF DMA TRANSFER REQUESTS
FUJITSU SEMICONDUCTOR CONFIDENTIAL
36
4.26. DMA Request Clear Register 27 : ICSEL27 (Interrupt
Clear SELect register 27)
The bit configuration of DMA request clear register 27 is shown below.
This bit is used to select the peripheral that has generated the interrupt to be cleared (assigned to interrupt
vector number #51).
ICSEL27: Address 043B
H
(Access : Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Reserved
OCU_SEL3
Initial value
0
0
0
0
0
0
0
0
Attribute R0,WX R0,WX R0,WX R0,WX R0,WX R0,WX R0,WX
R/W
[bit0] OCU_SEL3 (OCU_Selection3) : Interrupt clear selection bit for OCU4 / OCU5
OCU_SEL3
Clear target
0
16-bit OCU4
1
16-bit OCU5
MB91520 Series
MN705-00010-1v0-E
381