Fujitsu FR81S User Manual
CHAPTER 1: OVERVIEW
2. Features
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : OVERVIEW
FUJITSU SEMICONDUCTOR CONFIDENTIAL
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2.1. FR81S CPU Core
FR81S CPU core is shown.
32-bit RISC, load/store architecture, 5-stage pipeline
Maximum operating frequency: 80 MHz (Source oscillation = 4.0 MHz and 20 multiplied ( PLL clock
multiplication system ))
General-purpose register : 32-bit ×16 sets
16-bit fixed length instructions ( basic instruction ), 1 instruction per cycle
Instructions appropriate to embedded applications
Memory-to-memory transfer instruction
Bit processing instruction
Barrel shift instruction etc.
High-level language support instructions
Function entry/exit instructions
Register content multi-load and store instructions
Bit search instructions
Logical 1 detection, 0 detection, and change-point detection
Branch instructions with delay slot
Decrease overhead during branch process
Register interlock function
Easy assembler writing
Built-in multiplier and instruction level support
Signed 32-bit multiplication : 5 cycles
Signed 16-bit multiplication : 3 cycles
Interrupt ( PC/PS saving )
6 cycles ( 16 priority levels )
The Harvard architecture allows simultaneous execution of program and data access.
Instruction compatibility with the FR family
Built-in memory protection function ( MPU )
Eight protection areas can be specified commonly for instructions and the data.
Control access privilege in both privilege mode and user mode.
Built-in FPU (floating point arithmetic)
IEEE754 compliant
Floating-point register 32-bit × 16 sets
MB91520 Series
MN705-00010-1v0-E
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