Fujitsu FR81S User Manual
CHAPTER 11: I/O PORTS
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : I/O PORTS
FUJITSU SEMICONDUCTOR CONFIDENTIAL
10
4.2. Data Direction Register 00 to 19 : DDR00 to 19 (Data
Direction Register 00 to 19)
The bit configuration of data direction register 00 to 19 is shown below.
These registers set the I/O directions of the pins when they function as ports. If a pin is to be used for input
for a peripheral, the corresponding bit must be set for input.
DDR00 to DDR19 are key code target registers.
DDR00 to DDR19 : Address 0E00
H
, 0E01
H
,
(Access : Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
P[7:0]
Initial
value
0
0
0
0
0
0
0
0
Attribute
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
[bit7 to bit0] P (Port) : Data direction selection bits
These bits set the I/O direction of external pins P000, P001, ..., when the ports are in output mode.
DDR0.P[7:0] is for external pins P007 to P000
DDR1.P[7:0] is for external pins P017 to P010
DDR2.P[7:0] is for external pins P027 to P020
(A similar process continues)
The assignment is as shown above.
P[n]
Operation
0
Input (Initial value)
1
Output
DDR13.P7, DDR14.P[7:5, 1:0], DDR15.P[7:6] are reserved bits. Both writing to and reading from these
bits have no effect.
DDR13.P[6:5] are reserved bits in the dual clock products. Both writing to and reading from these bits have
no effect.
Some devices of the MB91520 series have ports missing. For details of which port is missing, see "1.16
Port function (General-Purpose I/O) Pins" in "CHAPTER:OVERVIEW". As for those bits allocated in the
missing ports, both writing and reading have no effect.
MB91520 Series
MN705-00010-1v0-E
405