Fujitsu FR81S User Manual
CHAPTER 13: EXTERNAL INTERRUPT INPUT
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : EXTERNAL INTERRUPT INPUT
FUJITSU SEMICONDUCTOR CONFIDENTIAL
6
4. Registers
This section explains registers of the external interrupt input.
Channel Base_addr
External pins
INT
0
0x0550
INT0_0
1
0x0550
INT1_0/ INT1_1
2
0x0550
INT2_0 / INT2_1
3
0x0550
INT3_0 / INT3_1
4
0x0550
INT4_0 / INT4_1
5
0x0550
INT5_0
6
0x0550
INT6_0
7
0x0550
INT7_0 / INT7_1
8
0x0554
INT8_0
9
0x0554
INT9_0 / INT9_1
10
0x0554
INT10_0
11
0x0554
INT11_0
12
0x0554
INT12_0
13
0x0554
INT13_0 / INT13_1
14
0x0554
INT14_0 / INT14_1
15
0x0554
INT15_0
Table 4-1 Registers Map
Address
Registers
Register function
+0
+1
+2
+3
0x0550
EIRR0
ENIR0
ELVR0
External interrupt factor register 0
External interrupt enable register 0
External interrupt request level register 0
0x0554
EIRR1
ENIR1
ELVR1
External interrupt factor register 1
External interrupt enable register 1
External interrupt request level register 1
MB91520 Series
MN705-00010-1v0-E
479