Fujitsu FR81S User Manual
CHAPTER 13: EXTERNAL INTERRUPT INPUT
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : EXTERNAL INTERRUPT INPUT
FUJITSU SEMICONDUCTOR CONFIDENTIAL
7
4.1. External Interrupt Factor Register 0/1 : EIRR0/EIRR1
(External Interrupt Request Register 0/1)
The bit configuration of external interrupt factor register 0/1 (EIRR0/EIRR1) is shown below.
This register holds information that an external interrupt factor has been generated.
EIRR0 : Address 0550
H
(Access: Byte, Half-word, Word)
EIRR1 : Address 0554
H
(Access: Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
ER7
ER6
ER5
ER4
ER3
ER2
ER1
ER0
Initial value
X
X
X
X
X
X
X
X
Attribute R(RM1),W R(RM1),W R(RM1),W R(RM1),W R(RM1),W R(RM1),W R(RM1),W R(RM1),W
[bit7 to bit0] ER7 to ER0 (External interrupt Request7 to 0) : External interrupt request bits
Flags to indicate that there is an interrupt request by INT external pin input. Writing "0" will clear it.
ERn
Meaning
Read
Write
0
No external interrupt request
Clear
1
External interrupt request exists
Does not influence operation
⋅
EIRR0:ER0 corresponds to INT0 pin, EIRR0:ER1 to INT1 pin, ..., EIRR0:ER7 to INT7 pin,
EIRR1:ER0 to INT8 pin, ..., EIRR1:ER7 to INT15 pin.
⋅
Writing "1" to these bits is invalid.
⋅
The values read with read-modify-write (RMW) instructions will always be "1".
⋅
When external interrupt detection condition is at "L" level or "H" level, the corresponding bit will be set
again if the external interrupt pin input is at an active level after clearing each bit in the EIRR register.
⋅
The factor bit in the interrupt factor register may be set by changing interrupt request level register.
Initialize the interrupt factor register after changing the interrupt request level register.
⋅
The value after resetting this register depends on the pin state after the reset.
⋅
This register will be initialized by all reset factors except recovery from standby (power shutdown)
when PMUCTLR:IOCTMD=1.
MB91520 Series
MN705-00010-1v0-E
480