Fujitsu FR81S User Manual
CHAPTER 13: EXTERNAL INTERRUPT INPUT
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : EXTERNAL INTERRUPT INPUT
FUJITSU SEMICONDUCTOR CONFIDENTIAL
8
4.2. External Interrupt Enable Register 0/1 : ENIR0/ENIR1
(ENable Interrupt request Register 0/1)
The bit configuration of external interrupt enable register 0/1 (ENIR0/ENIR1) is shown below.
This register enables external interrupt inputs.
ENIR0 : Address 0551
H
(Access: Byte, Half-word, Word)
ENIR1 : Address 0555
H
(Access: Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
EN7
EN6
EN5
EN4
EN3
EN2
EN1
EN0
Initial value
0
0
0
0
0
0
0
0
Attribute R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
[bit7 to bit0] EN7 to EN0 (interrupt ENable) : External interrupt enable bits
These bits perform mask controls of interrupt requests from external pin INT inputs.
ENn
Operations at the detection of an external pin
0
Interrupt request mask. Holds interrupt requests but does not output them.
(initial value)
1
Interrupt request enabled. Enables interrupt requests.
⋅
ENIR0:EN0 corresponds to INT0 pin, ENIR0:EN1 to INT1 pin, ..., ENIR0:EN7 to INT7 pin,
ENIR1:EN0 to INT8 pin, ..., ENIR1:EN7 to INT15 pin.
⋅
This register will be initialized by all reset factors except recovery from standby (power shutdown)
when PMUCTLR:IOCTMD=1.
MB91520 Series
MN705-00010-1v0-E
481