Fujitsu FR81S User Manual
CHAPTER 14: NMI INPUT
5. Operation
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER
: NMI INPUT
FUJITSU SEMICONDUCTOR CONFIDENTIAL
7
5. Operation
This section explains the operation of the NMI input.
NMI Interrupt Level
The NMI has the highest level among the user interrupts and cannot be masked. As an exception, the NMI is
masked after reset until the ILM is set by the CPU.
NMI External Pin
In stop mode, this pin detects the L level, and at other times it detects the falling edge.
Interrupt Request Output
The NMI request detector has an NMI flag that is set for an NMI request and is cleared only if an interrupt for
the NMI itself is accepted or reset occurs. The NMI flag cannot be read or written.
Read IRPR15H register to judge whether the NMI is caused by the NMIX external pin or the other factors.
For details of this register, see "INTERRUPT REQUEST BATCH READ".
Recovering From Stop Mode
When switching to stop mode, if an "L" level is input to the NMIX, an NMI request is output to the interrupt
controller and the CPU recovers from stop mode. If the CPU switches to stop mode without returning the
input level of the NMIX pin to the "H" level after the NMI processing routine has finished in normal mode
(not stop mode), the CPU recovers immediately after switching to stop mode (see [2] in Figure 5-1).
Similarly, the power shut-down will not be controlled when the status changes to the stop mode (power
shut-down) without setting the NMIX pin to the "H" level. Return the input level of the NMIX pin to the "H"
level before entering stop mode so that the input level of the NMIX pin is set to the "L" level in stop mode.
Figure 5-1 Recovering from Stop Mode
*: The watch mode and the watch mode (power shut-down) are similarly controlled.
Operation status
NMIX input
NMIX input
Operation status
Recovery from stop at
"L" level after falling edge
NMI processing
routine
"
L
"
level detected and recover from stop
mode soon after entering stop mode
NMIX input
MB91520 Series
MN705-00010-1v0-E
494