Fujitsu FR81S User Manual
MB91520 Series
FUJITSU SEMICONDUCTOR LIMITED
FUJITSU SEMICONDUCTOR CONFIDENTIAL
iv
Term
Explanation
32-bit peripheral
bus
A 32-bit width, low-speed internal bus.
It connects to various types of peripherals.
16-bit peripheral
bus (R-bus)
A 16-bit width, low-speed internal bus.
It connects to various types of peripherals. The 32-bit width access to this bus is divided into
16 bits
16 bits
×
2.
External bus
(External bus)
8/16-bit width, low-speed external bus. It connects to memory devices, ASIC and others. This
series is the bus master, and a device connected to the external bus is a bus slave.
Main clock
(MCLK)
This is the reference clock for LSI operation, and it is supplied from the high-speed system
oscillator.
It is connected to the timer for main oscillation stabilization wait, the clock generator (PLL)
and others.
Sub clock
(SBCLK)
This is the reference clock for LSI operation, and it is supplied from the low-speed system
oscillator.
It is connected to the timer for sub oscillation stabilization wait and others.
It can be used by the dual clock products only.
CR oscillation
The clock for watchdog timer 1 (hardware watchdog)
PLL clock
(PLLCLK)
The main clock is multiplied by PLL.
CPU clock
(CCLK)
The clock for peripherals operating under the XBS.
On-chip
bus clock
(HCLK)
The clock for peripherals operating under the on-chip bus.
Peripheral clock
(PCLK)
The clock for peripherals operating under the 32-bit peripheral bus and 16-bit peripheral bus.
External
bus clock
(TCLK)
The reference clock for an external bus interface connected to the X-bus and for the external
clock output. It is generated from the base clock by the clock generator.
Main clock mode
The operation mode based on the main clock. The main clock mode has the main RUN, main
sleep, main stop, oscillation stabilization wait RUN, oscillation stabilization wait reset, and
program reset state.
Main RUN
The main clock mode is selected, and all circuits are operable.
Oscillation
stabilization
wait time
When the clock is switched from the stop state to the oscillation state, the clock takes the
oscillation stabilization time. During the oscillation stabilization wait time, the clock is not
supplied.
OCD
The on-chip debugger for this series
OCDU
The OCD interface built in this product.
OCD tool
The OCD tool can be connected to the DEBUG I/F pin of this device.
Chip reset
sequence
In the chip reset sequence, the connection of OCD tool is checked. It takes (1026+3) PCLK
cycles.
Power-shutdown
The power supply to the target circuit is stopped, and power consumption is decreased.
Always
power
supply ON block
It is not a target division for the power-shutdown.
PMU
Power
management unit
The power shutdown is controlled. PMU exists in always ON block.
MN705-00010-1v0-E
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