Fujitsu FR81S User Manual
CHAPTER 17: PPG
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER
: PPG
FUJITSU SEMICONDUCTOR CONFIDENTIAL
23
4.5. PPG Control Status Register2 : PCN200 to PCN247
The bit configuration of the PPG control status register2 is shown.
The PPG control status register2 (PCN2) controls the operation and status of the PPG.
PPG control status register2 (PCN2): Address Base_addr + 08
H
(Access: Byte,
Half-word, Word)
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Reserved Reserved
LFPR
HFPR
CMDSEL
CMD
TPC
STRD
Initial value
0
0
0
0
0
0
0
0
Attribute R0/W0
R0/W0
R/W
R/W
R/W
R/W
R/W
R/W
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Reserved Reserved Reserved Reserved Reserved REMP
SREMP
IRS2
Initial value
0
0
0
0
0
1
1
0
Attribute R0/W0
R0/W0
R0/W0
R0/W0
R0/W0
R
R
R/W
[bit15, bit14] Reserved bits
⋅
The reading value of these bits is always "0".
⋅
These bits must always be written to "0".
[bit13] LFPR : Low format pulse polarity selection bit
LFPR
Explanation
0
Output from Low pulse
(When PCN.OSEL=1: the High pulse output)
1
Output from High pulse
(When PCN.OSEL=1: the Low pulse output)
*: In PPG4 to PPG47, the communication function is not built into. The reading value of this bit is always
"0". This bit must always be written to "0".
[bit12] HFPR : High format pulse polarity selection bit
HFPR
Explanation
0
Output from Low pulse
(When PCN.OSEL=1: the High pulse output)
1
Output from High pulse
(When PCN.OSEL=1: the Low pulse output)
*: In PPG4 to PPG47, the communication function is not built into. The reading value of this bit is always
"0". This bit must always be written to "0".
[bit11] CMDSEL : PPG communication mode data read selection bit
CMDSEL
Explanation
0
Output from LSB bit position of PCMDDT set in PCMDWD
1
Output from MSB bit position of PCMDDT set in PCMDWD
*: In PPG4 to PPG47, the communication function is not built into. The reading value of this bit is always
"0". This bit must always be written to "0".
MB91520 Series
MN705-00010-1v0-E
564