Fujitsu FR81S User Manual
CHAPTER 17: PPG
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER
: PPG
FUJITSU SEMICONDUCTOR CONFIDENTIAL
25
4.6. Start Delay Value Setting Register : PSDR0 to PSDR47
The bit configuration of the Start Delay value setting register is shown.
The Start Delay value setting register (PSDR) sets the delay value to shift the phase of PPG output
waveform.
Start Delay value setting register (PSDR): Address Base_addr + 0A
H
(Access:
Half-word, Word)
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
D15
D14
D13
D12
D11
D10
D9
D8
Initial value
0
0
0
0
0
0
0
0
Attribute
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
D7
D6
D5
D4
D3
D2
D1
D0
Initial value
0
0
0
0
0
0
0
0
Attribute
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
[bit15 to bit0] D15 to D0 : Start Delay value setting bits
The phase from the activation trigger generation to PPG waveform output is adjusted according to the
following calculations.
(Start Delay value setting register + 1) × Count clock
Notes:
⋅
If the PPG output waveform selection bit (PCN.OWFS)="0" (Normal Wave Form) is selected, the delay
value is the set value of the Start Delay value setting register.
⋅
If the PPG output waveform selection bit (PCN.OWFS)=1 (Center Aligned Wave Form) is selected, the
delay value is doubling the set value of the Start Delay value setting register.
⋅
Be sure to access this register by the word (16-bit) format. If the byte is accessed to this register, the
value is not written at an upper and lower bit position.
MB91520 Series
MN705-00010-1v0-E
566