Fujitsu FR81S User Manual
CHAPTER 17: PPG
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER
: PPG
FUJITSU SEMICONDUCTOR CONFIDENTIAL
30
4.11. PPG Communication Mode Low Format Duty Setting
Register : PLDUT0 to PLDUT3
The bit configuration of the PPG communication mode Low format duty setting register is
shown.
The PPG communication mode Low format duty setting register (PLDUT) sets the duty for the Low
format.
*: In PPG4 to PPG47, the communication function is not built into. The reading value of this bit is always
"0". This bit must always be written to "0".
PPG communication mode Low format duty setting register (PLDUT):
Address Base_addr + 16
H
(Access: Half-word, Word)
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
D15
D14
D13
D12
D11
D10
D9
D8
Initial value
X
X
X
X
X
X
X
X
Attribute
W
W
W
W
W
W
W
W
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
D7
D6
D5
D4
D3
D2
D1
D0
Initial value
X
X
X
X
X
X
X
X
Attribute
W
W
W
W
W
W
W
W
[bit15 to bit0] D15 to D0 : PPG communication mode Low format duty setting bits
When borrow of the counter is generated, the value is automatically transferred from the PPG
communication mode Low format duty setting register to the counter.
Notes:
⋅
Be sure to set a value that is smaller than the value set to the PPG communication mode Low format
cycle setting register (PLCSR) to the PPG communication mode Low format duty setting register.
⋅
In the PPG communication mode, the setting of PPG output waveform selection bit (PCN.OWFS) and
mode selection bit (PCN.MDSE) does not influence operation.
⋅
Be sure to access this register by the word (16-bit) format. If the byte is accessed to this register, the
value is not written at an upper and lower bit position.
MB91520 Series
MN705-00010-1v0-E
571