Fujitsu FR81S User Manual
CHAPTER 18: WATCHDOG TIMER
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : WATCHDOG TIMER
FUJITSU SEMICONDUCTOR CONFIDENTIAL
15
4.5. Watchdog Timer 1 Clear Register : WDTCPR1
(WatchDog Timer Clear Pattern Register 1)
The bit configuration of the watchdog timer 1 clear register is shown.
This register clears watchdog timer 1 (makes the watchdog timer 1 defers issuing a reset signal).
WDTCPR1 : Address 003F
H
(Access: Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
CPAT[7:0]
Initial value
0
0
0
0
0
0
0
0
Attribute R0,W
R0,W
R0,W
R0,W
R0,W
R0,W
R0,W
R0,W
[bit7 to bit0] CPAT[7:0] (Clear PATtern) : Watchdog timer 1 clear
Watchdog timer 1 activates after the reset is released. The watchdog timer is cleared after being activated by
writing "0xA5". When a value other than "0xA5" is written, the watchdog reset 1 is issued at that time. The
value read out from this register is always "0x00"regardless of the value written.
MB91520 Series
MN705-00010-1v0-E
624