Fujitsu FR81S User Manual
CHAPTER 19: BASE TIMER
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER
: BASE TIMER
FUJITSU SEMICONDUCTOR CONFIDENTIAL
37
4.5.2. Data Buffer Registers 0, 1 : BTxDTBF (Base Timer 0/1
DaTa BuFfer register)
The bit configuration of data buffer registers 0, 1 (BTxDTBF) is shown below.
These registers are used to read out the measurement value of the 16/32-bit PWC timer and the up counter
value.
Notes:
⋅
These registers must be accessed in 16-bit mode.
⋅
These registers will also be initialized when reset mode is set (writing of BTxTMCR:FMD = 000).
BTxDTBF : Address Base_addr + 0A
H
(Access: Half-word)
bit15
bit14
- - -
bit2
bit1
bit0
D[15:0]
Initial value
0
0
- - -
0
0
0
Attribute R,WX
R,WX
- - -
R,WX
R,WX
R,WX
[bit15 to bit0] D[15:0] (Data) : Data bits
These registers are used to read out the measurement value of the 16/32-bit PWC timer and the up counter
value. The value read from these registers is different in the single measurement mode and continuous
measurement mode.
⋅
Single measurement mode: The up counter value is read during counting and the measurement result is
read after the measurement completion.
⋅
Continuous measurement mode: The value measured previously is read both during counting and after
the measurement completion. The up counter value cannot be read.
The following values are set to these registers when two channels of a 16-bit PWC timer are cascaded and it is
used as the 32-bit PWC timer.
⋅
Value of even-number channel data buffer register (BTxDTBF): Value of lower 16-bit
⋅
Value of odd-number channel data buffer register (BTxDTBF): Value of upper 16-bit
In the 32-bit timer mode, read these registers value in the following order.
1. Even-channel data buffer register (BTxDTBF)
2. Odd-channel data buffer register (BTxDTBF)
MB91520 Series
MN705-00010-1v0-E
670