Fujitsu FR81S User Manual
CHAPTER 19: BASE TIMER
5. Operation
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER
: BASE TIMER
FUJITSU SEMICONDUCTOR CONFIDENTIAL
46
5.3.3. 32-bit Mode Operation
This section explains 32-bit mode operation.
After setting the 32-bit mode when the reload timer or PWC timer is started with the control of the
even-number channel, the timer/counter of the even-number channel operates with lower 16-bit and the
timer/counter of the odd-number channel operates with upper 16-bit.
The 32-bit mode operation depends on the setting of the even-number channel. Thus, the setting of the
odd-number channel (excepting the cycle setting register for the reload timer) is ignored. Timer activation,
waveform output and interrupt signal also apply the setting of the even-number channel. (The odd-number
channel is masked with the value fixed to L.)
For the configuration, see Figure 5-11 and Figure 5-28 .
MB91520 Series
MN705-00010-1v0-E
679