Fujitsu FR81S User Manual

CHAPTER 19: BASE TIMER

5. Operation

FUJITSU SEMICONDUCTOR LIMITED

CHAPTER

: BASE TIMER

FUJITSU SEMICONDUCTOR CONFIDENTIAL

5.5.4. Interrupt

This section explains interrupts.

An interrupt request is generated in one of the following events:

⋅

An activation trigger is detected. (trigger interrupt request)

⋅

The value of the 16-bit down counter matches the value of (the base timer x duty setting register

(BTxPDUT)) (duty match interrupt request).

⋅

An underflow occurs (underflow interrupt request).

Table 5-4 Conditions for Interrupt Generation

Interrupt request

flag

Permission of

interrupt request

Interrupt request clear

Trigger interrupt request

BTxSTC:TGIR = 1

BTxSTC:TGIE = 1

Set the TGIR bit of BTxSTC

to "0".

Duty match interrupt request

BTxSTC:DTIR=1

BTxSTC:DTIE=1

Set the DTIR bit of BTxSTC

to "0".

Underflow interrupt request

BTxSTC:UDIR = 1

BTxSTC:UDIE = 1

Set the UDIR bit of BTxSTC

to "0".

Notes:

⋅

Once the generation of an interrupt request is enabled while the interrupt request flag is "1", an interrupt

request will be issued when the interrupt is enabled. To enable the generation of an interrupt request,

perform one of the following operations:

⋅

Clear the current interrupt request before enabling the generation of an interrupt request.

⋅

Clear the current interrupt request when enabling the interrupt.

⋅

Either clear the current interrupt request after disabling the generation of an interrupt request or clear the

current interrupt request within the interrupt processing routine.

⋅

For interrupt vector numbers used when issuing an interrupt request, see "List of Interrupts Vector" in

entitled "APPENDIX".

⋅

Set the interrupt level corresponding to the interrupt vector number in one of the interrupt control

registers (ICR00 to ICR47). For information on interrupt level setting, see the chapter entitled

"CHAPTER: INTERRUPT CONTROL (INTERRUPT CONTROLLER)".

MB91520 Series

MN705-00010-1v0-E

700