Fujitsu FR81S User Manual
CHAPTER 19: BASE TIMER
5. Operation
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER
: BASE TIMER
FUJITSU SEMICONDUCTOR CONFIDENTIAL
68
5.5.5. Precautions for Using this Device
This section explains precautions for using this device.
Note the following when using the 16-bit PWM timer:
Notes on Program Setting
⋅
Change the following bits of the timer control register (BTxTMCR) only after stopping the 16-bit down
counter by resetting the CTEN bit to "0"(CTEN=0).
⋅
CKS2 to CKS0 bits
⋅
EGS1 and EGS0 bits
⋅
FMD2 to FMD0 bits
⋅
MDSE bit
⋅
All registers are initialized when the FMD2 to FMD0 bits of the base timer x timer control register
(BTxTMCR) are set to "000" to select reset mode.
⋅
Before the base timer function can be changed, the base timer must be reset once. Except when rewriting
the FMD2 to FMD0 bits of the base timer x timer control register (BTxTMCR) after reset, be sure to
clear FMD2 to FMD0 bits to "000" to select the reset mode, and then select a base timer function using
the FMD2 to FMD0 bits again.
⋅
To set 16-bit PWM timer cycles or duties, proceed as follows:
1. Select the 16-bit PWM timer as the base timer function by setting the FMD2 to FMD0 bits of the base
timer x timer control register (BTxTMCR) to "001"(FMD2 to FMD0=001).
2. Set the cycle in the base timer x cycle setting register (BTxPCSR).
3. Set the duty in the base timer x duty setting register (BTxPDUT).
Notes on Operation
⋅
If the count timing of the 16-bit down counter and the load timing occur at the same time, the load
operation is given precedence.
⋅
When a 16-bit PWM timer reactivation trigger is detected when counting ends in one-shot mode, the
value in the base timer x cycle setting register (BTxPCSR) is loaded to the 16-bit down counter, which
then starts counting.
⋅
A different signal (external clock, external activation trigger, wave form) I/O operation can be selected
using the base timer I/O selection function.
Notes on Interrupts
If an instruction to clear the interrupt request flag and an instruction to change the interrupt request flag to "1"
occur at the same time, the flag clear instruction is ignored. The interrupt request flag is held to "1".
MB91520 Series
MN705-00010-1v0-E
701