Fujitsu FR81S User Manual
CHAPTER 19: BASE TIMER
5. Operation
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER
: BASE TIMER
FUJITSU SEMICONDUCTOR CONFIDENTIAL
93
5.7.4. Interrupt
This section explains interrupt of the base timer.
An interrupt request is generated in one of the following events:
⋅
An overflow occurs. (Overflow interrupt request)
⋅
The measurement ends. (Measurement end interrupt request)
Table 5-7 Interrupt Occurrence Conditions
Interrupt request
Interrupt request flag
Permission of
interrupt request
Interrupt request clear
Overflow interrupt request
BTxSTC:OVIR=1
BTxSTC:OVIE=1
Set the OVIR bit of
BTxSTC to "0".
Measurement end
interrupt request
BTxSTC:EDIR=1
BTxSTC:EDIE=1
Read BTxDTBF
Notes:
⋅
Once the generation of an interrupt request is enabled while the interrupt request flag is "1", an interrupt
request will be issued when the interrupt is enabled.
⋅
To enable the generation of an interrupt request, perform one of the following operations:
⋅
Clear the current interrupt request before enabling the generation of an interrupt request.
⋅
Clear the current interrupt request when enabling the interrupt.
⋅
Either clear the current interrupt request after disabling the generation of an interrupt request or clear
the current interrupt request within the interrupt processing routine.
⋅
For interrupt vector numbers used for issuing an interrupt request, see "List of Interrupts Vector" in
entitled "APPENDIX".
⋅
Set the interrupt level corresponding to the interrupt vector number in one of the interrupt control
registers (ICR00 to ICR47). For information on interrupt level setting, see the chapter entitled
"CHAPTER: INTERRUPT CONTROL (INTERRUPT CONTROLLER)".
MB91520 Series
MN705-00010-1v0-E
726