Fujitsu FR81S User Manual

CHAPTER 20: RELOAD TIMER 

 

 

3. Configuration 
 

FUJITSU SEMICONDUCTOR LIMITED 

CHAPTER : RELOAD TIMER 
FUJITSU SEMICONDUCTOR CONFIDENTIAL 

5 

This section explains the configuration of the reload timer. 

Figure 3-1 Block Diagram of Reload Timer (1 Channel, Details) 

 

 

TOUT

INT

MOD0

MOD1

RELD

INTE

UF

EF

OUTL

CNTE

TMR

TMRLRA

Read/Write

Read/Write

Read/Write

Read only

TMRLRB

Count

comparator

Count control

Buffer

P

e

rip

h

e

ra

l

b

u

s

Reload

C

a

p

tu

re

m

o

d

e

Mode control

R

el

oad s

el

ec
tor

CSL2

CSL1

CSL0

GATE

TRGM1

TRGM0

TMCSR

bit in any sequence

TRG

Unused

Compare mode

End One-shot

Compare

result

Underflow

Enable a count

Trigger

Peripheral

clock

Capture

Trigger

Gate

Output

FF

Prescaler

Clock selector

Input

+

Synchronization

FF

Edge

control

Gate

control

Peripheral

clock

Peripheral

clock

TTRG

Select

Select

TIN 

MN705-00010-1v0-E

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