Fujitsu FR81S User Manual
CHAPTER 20: RELOAD TIMER
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : RELOAD TIMER
FUJITSU SEMICONDUCTOR CONFIDENTIAL
FUJITSU SEMICONDUCTOR CONFIDENTIAL
13
4.3. 16-bit Timer Reload Register A, 16-bit Timer Reload
Register B : TMRLRA, TMRLRB(16bit TiMer ReLoad
Register A/B)
Register A/B)
The bit configuration of 16-bit timer reload register A and 16-bit timer reload register B is
shown below.
shown below.
This register sets the count initial value and other items.
Always perform 16-bit access to this register.
TMRLRA : Address Base_addr + 00
H
(Access : Half-word)
bit15
bit14
....
bit2
bit1
bit0
TMRLRA[15:0]
Initial value
X
X
....
X
X
X
Attribute
R/W
R/W
....
R/W
R/W
R/W
TMRLRB : Address Base_addr + 04
H
(Access : Half-word)
bit15
bit14
....
bit2
bit1
bit0
TMRLRB[15:0]
Initial value
X
X
....
X
X
X
Attribute
R,W
R,W
....
R,W
R,W
R,W
[bit15 to bit0] TMRLRA[15:0] (TiMer ReLoad Register A) : 16-bit reload setting register A
[bit15 to bit0] TMRLRB[15:0] (TiMer ReLoad Register B) : 16-bit reload setting register B
The TMRLRA register is where the count initial value is hold. The TMRLRA can be used in all mode with
regardless of the bit15, bit14:MOD[1:0] setting in the TMCSR register.
regardless of the bit15, bit14:MOD[1:0] setting in the TMCSR register.
The TMRLRB is to be used by the bit15, bit14:MOD[1:0] setting in the TMCSR register specified
following:
following:
Mode
MOD[1:0]
TMRLRB functions
Single mode
00
Not used
Dual mode
01
H width (when OUTL=0) counter value
Compare mode
10
Compare register (when H width setting is OUTL=0)
Capture mode
11
Capture register (TMR value upon retrigger input)
When using as a counter value, underflow is generated if 1 count is set when writing 0x0000 and 65,536 is
set when writing 0xFFFF.
set when writing 0xFFFF.
H width and L width of the timer output waveform (TOUT) are determined by the MOD[1:0] (bit15, bit14
of the TMCSR register), RELD (bit4 of the TMCSR register), and OUTL (bit5 of the TMCSR register) bit
setting as well as the TMRLRA/B register value. H width and L width setting of the waveform(TOUT) to
be outputted is shown in the table below.
of the TMCSR register), RELD (bit4 of the TMCSR register), and OUTL (bit5 of the TMCSR register) bit
setting as well as the TMRLRA/B register value. H width and L width setting of the waveform(TOUT) to
be outputted is shown in the table below.
MB91520 Series
MN705-00010-1v0-E
740