Fujitsu FR81S User Manual
CHAPTER 20: RELOAD TIMER
5. Operation
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : RELOAD TIMER
FUJITSU SEMICONDUCTOR CONFIDENTIAL
FUJITSU SEMICONDUCTOR CONFIDENTIAL
30
5.2.4. Generation of Interrupt Requests
Generation of interrupt requests is shown below.
When bit3:INTE bit of the TMCSR register is "1", if bit2:UF bit/bit7:EF bit are set, an interrupt request is
generated. In interval timer mode, the UF bit and the EF bit will be set under the following conditions.
generated. In interval timer mode, the UF bit and the EF bit will be set under the following conditions.
⋅ UF bit is set: A counter underflow occurred
⋅ EF bit is set: A capture input occurred in capture mode
⋅ EF bit is set: A capture input occurred in capture mode
When a set of bit2:UF bit of the TMCSR register and a clear of the UF bit by writing "0" occurred
concurrently, writing "0" to the UF bit will be invalid and the UF bit will be set. When a set of bit7:EF bit
and a clear of the EF bit by writing "0" occurred concurrently, writing "0" to the EF bit will be invalid and
the EF bit will be set.
concurrently, writing "0" to the UF bit will be invalid and the UF bit will be set. When a set of bit7:EF bit
and a clear of the EF bit by writing "0" occurred concurrently, writing "0" to the EF bit will be invalid and
the EF bit will be set.
The following is the example of generation of interrupt requests.
Figure 5-6 Example of UF Interrupt Request Output Operation
Count clock
Counter value
Underflow
Interrupt request
UF bit
UF interrupt request output operation (bit4:RELD= "1" and bit3:INTE="1" of TMCSR register)
Reload data
-1
0x0000
0x0001
-1
-1
MB91520 Series
MN705-00010-1v0-E
757