Fujitsu FR81S User Manual
CHAPTER 20: RELOAD TIMER
5. Operation
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : RELOAD TIMER
FUJITSU SEMICONDUCTOR CONFIDENTIAL
FUJITSU SEMICONDUCTOR CONFIDENTIAL
33
5.3.1. Single One-shot Operation
The single one-shot operation is shown below.
When bit15, bit14:MOD[1:0]=00 and bit4:RELD of the TMCSR register =0, the single one-shot operation
will be performed in which the timer stops with 0xFFFF by an occurrence of an underflow.
will be performed in which the timer stops with 0xFFFF by an occurrence of an underflow.
In the single one-shot configuration, if an underflow occurs, the following operation will be performed.
⋅ Sets the UF bit of the TMCSR register.
⋅ When interrupts are enabled (bit3:INTE=1 of TMCSR register), an interrupt occurs.
⋅ Stops the count with 0xFFFF.
⋅ Initializes TOUT output.
⋅ Timer is waiting for a trigger.
⋅ When interrupts are enabled (bit3:INTE=1 of TMCSR register), an interrupt occurs.
⋅ Stops the count with 0xFFFF.
⋅ Initializes TOUT output.
⋅ Timer is waiting for a trigger.
For the single one-shot timer, TMRLRA turns to the initial value of the counter when a reload took place.
TMRLRB is not used.
TMRLRB is not used.
MB91520 Series
MN705-00010-1v0-E
760