Fujitsu FR81S User Manual
CHAPTER 20: RELOAD TIMER
5. Operation
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : RELOAD TIMER
FUJITSU SEMICONDUCTOR CONFIDENTIAL
FUJITSU SEMICONDUCTOR CONFIDENTIAL
35
5.3.2. Single Reload Operation
The single reload operation is shown below.
When bit15, bit14:MOD[1:0] of the TMCSR register =00, and bit4:RELD of the TMCSR register =1, the
single reload operation will be performed.
single reload operation will be performed.
In single reload operation, a value will be loaded from TMRLRA to the timer by trigger input, a down count
(decrementing the count) will start. When an underflow occurs, the value is reloaded from TMRLRA again
and the down count operation continues. The value of TMRLRA represents the time the timer will reload.
The TMRLRB register is not used. In single reload configuration, if an underflow occurs, the following
operation will be performed.
(decrementing the count) will start. When an underflow occurs, the value is reloaded from TMRLRA again
and the down count operation continues. The value of TMRLRA represents the time the timer will reload.
The TMRLRB register is not used. In single reload configuration, if an underflow occurs, the following
operation will be performed.
⋅ Sets bit2:UF bit of the TMCSR register.
⋅ When interrupts are enabled (bit3:INTE=1 of TMCSR register), an interrupt occurs.
⋅ Loads TMRLRA register onto the counter.
⋅ Inverts TOUT output.
⋅ Continues decrementing count.
⋅ When interrupts are enabled (bit3:INTE=1 of TMCSR register), an interrupt occurs.
⋅ Loads TMRLRA register onto the counter.
⋅ Inverts TOUT output.
⋅ Continues decrementing count.
MB91520 Series
MN705-00010-1v0-E
762