Fujitsu FR81S User Manual

CHAPTER 20: RELOAD TIMER

5. Operation

FUJITSU SEMICONDUCTOR LIMITED

CHAPTER : RELOAD TIMER
FUJITSU SEMICONDUCTOR CONFIDENTIAL

Figure 5-16 Compare Reload Operation (1 / 2)

TMRLRA + 1

TMRLRB

TMRLRA + 1

TMRLRB

TMRLRA + 1

TMRLRB

TMRLRA

TMRLRA+1

TMRLRA

TMRLRA+1

• Sets TMRLRB < TMRLRA

TOUT

Count clock

Underflow

UF bit

EF bit

Reload

Activation trigger

Counting from

count

Compare reload function (TMRLRB < TMRLRA) trigger input

• Sets TMRLRB > TMRLRA

Compare reload function (TMRLRB > TMRLRA) trigger input

(for OUTL=0)

comparison match

reloaded by timer

(for OUTL=0)

When the register relation is as described above, the TOUT output is the L level until TMR and TMRLRB

match after loading to the timer. When down counting from the comparison match (TMR=TMRLRB), the

level is H until the TOUT output is inverted and an underflow occurs. When an underflow occurs the

TOUT output will be initialized. When an under flow occurs, the timer will reload from TMRLRA and

continue counting operation (for OUTL="0").

When the register relation is as described above, the TOUT output is the H level after an activation

trigger is generated and an underflow occurs because TMR is always smaller than TMRLRB. The level

will remain to be H even when an underflow occurs. When an underflow occurs, the timer will load from

TMRLRA and continue counting operation (for OUTL="0").

MB91520 Series

MN705-00010-1v0-E

772