Fujitsu FR81S User Manual
CHAPTER 20: RELOAD TIMER
6. Application Note
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : RELOAD TIMER
FUJITSU SEMICONDUCTOR CONFIDENTIAL
FUJITSU SEMICONDUCTOR CONFIDENTIAL
67
6.5. PWC
PWC is shown below.
PWC is the feature to measure the time interval between triggers to input.
An activation trigger launches a load of a value from TMRLRA onto the counter and executes a down count
operation. A trigger input during a count enables the counter value at that time to be captured onto
TMRLRB, which allows measuring the time interval between triggers to input.
operation. A trigger input during a count enables the counter value at that time to be captured onto
TMRLRB, which allows measuring the time interval between triggers to input.
[Configuration] To use the timer as PWC, configure as follows.
TMCSR
TMRLRA TMRLRB
MOD
[1:0]
TRGM
[1:0]
CSL
[2:0]
GATE EF OUTL RELD INTE UF CNTE TRG
(A)
(B)
11
*1
*2
0
-
*3
*4
*5
-
1
S
(A):
The count initial value when activation trigger occurs/The reload value at an underflow (when RELD=1)
S :Use at timer activation
-:Does not influence operation
*1: TIN effective edge setting
-:Does not influence operation
*1: TIN effective edge setting
TRGM[1:0]= 00------Does not detect external trigger edge
TRGM[1:0]= 01------Rising edge
TRGM[1:0]= 10------Falling edge
TRGM[1:0]= 11------Both edges
*2:Count clock division setting
CSL[2:0]= 000------Division of peripheral clock (PCLK) by 2
CSL[2:0]= 010------Division of peripheral clock (PCLK) by 8
CSL[2:0]= 011------Division of peripheral clock (PCLK) by 16
CSL[2:0]= 100------Division of peripheral clock (PCLK) by 32
CSL[2:0]= 101------Division of peripheral clock (PCLK) by 64
*3:TOUT output polarity setting
OUTL= 0------Initial value L=> Count L from TMRLRA => Invert whenever an underflow occurs
OUTL= 1------Initial value H=> Count H from TMRLRA => Invert whenever an underflow occurs
*4:Reload setting when an underflow occurs
RELD= 0------One-shot mode
RELD= 1------Reload mode
*5:Interrupt request enable setting
INTE= 0------Interrupt disabled
INTE= 1------Interrupt enabled
[Timer activation] Follow the steps below to activate the timer.
⋅ Input an activation trigger (a write of "1" to TRG bit or an input of effective external edge from TIN pin)
While down counting, the counter value will be captured onto the TMRLRB whenever a trigger input
occurs. The time interval between edges of the triggers to input will be obtained by the following
formula.
occurs. The time interval between edges of the triggers to input will be obtained by the following
formula.
T = (The set value for TMRLRA - The captured value for TMRLRB) × Peripheral clock (PCLK)
cycle × Division ratio set with CSL
cycle × Division ratio set with CSL
MB91520 Series
MN705-00010-1v0-E
794