Fujitsu FR81S User Manual
CHAPTER 23: 32-BIT INPUT CAPTURE
3. Configuration
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER
: 32-BIT INPUT CAPTURE
FUJITSU SEMICONDUCTOR CONFIDENTIAL
5
3. Configuration
This section explains the configuration of the 32-bit input capture.
Figure 3-1 Block Diagram (detailed; per 2 channel)
Edge detect
EGI40/41
ICP4
ICE4
ICS
External Pin ICU4 /
LIN synch Field MFS ch4
LIN synch Field MFS ch4
ICU4 interrupt
From 32bit free-
run timer
ICS
ICS
Cycle measurement data register
4
(MSCY4)
Measurement
counter 4
Input capture
Data register 4
(IPCP4)
cycle・pulse
Measurement control
cycle
calculate
control
PLS4
CYC4
MSC
MSC
MSC4
MSC
MSO4
MSC
CH4
OVC4
MSC
OVP4
MSC
Edge detect
EGI50/51
ICP5
ICE5
ICS
ICU5 interrupt
from 32bit free-
run timer
ICS
ICS
Cycle measurement data register
5 (MSCY5)
Measurement
counter 5
Input capture
Data register 5
(IPCP5)
cycle・pulse
Measurement control
cycle
calculate
control
PLS5
CYC5
MSC
MSC
MSC5
MSC
MSC5
MSC
CH5
OVC5
MSC
OVP5
MSC
External pin ICU5 /
LIN synch Field MFS ch5
LIN synch Field MFS ch5
MB91520 Series
MN705-00010-1v0-E
880