Fujitsu FR81S User Manual
CHAPTER 23: 32-BIT INPUT CAPTURE
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER
: 32-BIT INPUT CAPTURE
FUJITSU SEMICONDUCTOR CONFIDENTIAL
14
4.6. Cycle and Pulse Width Measurement Control Register
(Lower bit) : MSCL
This section shows the cycle and pulse width measurement control register (lower bit).
This register is used to control the input capture.
x: Channel number 4, 6, 8
y: Channel number 5, 7, 9
MSCL45 (Input capture 45): Address 0F8B
H
(Access: Byte, Half-word, Word)
MSCL67 (Input capture 67): Address 0F8F
H
(Access: Byte, Half-word, Word)
MSCL89 (Input capture 89): Address 0FFF
H
(Access: Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
-
-
-
-
-
-
MSCy
MSCx
Initial value
1
1
1
1
1
1
0
0
Attribute R0,WX
R0,WX
R0,WX
R0,WX
R0,WX
R0,WX
R/W
R/W
[bit7 to bit2] : Undefined
The read value is always "1". Writing has no effect on operation.
[bit1, bit0] MSCn : Operation mode setting
MSCn
Explanation
0
Input capture operation
1
Measurement operation of cycle and pulse width
⋅
These bits select the operation mode when the edge of external input ICUn is detected.
* MSCn : The number of n corresponds to the channel number of the input capture.
MB91520 Series
MN705-00010-1v0-E
889