Fujitsu FR81S User Manual
CHAPTER 23: 32-BIT INPUT CAPTURE
5. Operation
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER
: 32-BIT INPUT CAPTURE
FUJITSU SEMICONDUCTOR CONFIDENTIAL
17
5.2. Edge Detection Specifications for Input Capture And
Their Operations
This section shows edge detection specifications for the input capture and their operations.
Figure 5-2 Example of the Edge Detection Specifications Operation
⋅
When rising edge is selected
(1) Rising edge of the input signal is detected.
(2) Free-run counter value is recorded to the capture register (capture).
(3) Input capture interrupt is generated.
⋅
When falling edge is selected
(4) Falling edge of the input signal is detected.
(5) Free-run counter value is recorded to the capture register (capture).
(6) Input capture interrupt is generated.
⋅
Both edges
(7) Rising edge of the input signal is detected.
(8) Free-run counter value is recorded to the capture register (capture).
(9) Input capture interrupt is generated.
(10) Interrupt request flag ((ICS45.ICP4), (ICS45.ICP5), (ICS67.ICP6), (ICS67. ICP7), ....) is cleared
using software.
Count value
of free-run
timer 0
Time
Count value A
Count value B
Count value C
Count value D
Falling
edge
Interrupt
request
Input
capture
Rising
edge
Capture data
register
Interrupt
request
Input
capture
Capture data
register
Interrupt
request
Input
capture
Capture data
register
Both
edges
Clearing flag
by software
(1)
(2)
(5)
(4)
(3)
(8)
(7)
(6)
(9)
(10)
(11)
(12)
(13)
FFFFFFFFH
00000000H
Overflow
(IVF)
(1)
(2)
(5)
(4)
(3)
(8)
(7)
(6)
(9)
(10)
(11)
(12)
(13)
Enable free-run
timer operation
Count value of
free-run timer 3
MB91520 Series
MN705-00010-1v0-E
892