Fujitsu FR81S User Manual
CHAPTER 23: 32-BIT INPUT CAPTURE
5. Operation
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER
: 32-BIT INPUT CAPTURE
FUJITSU SEMICONDUCTOR CONFIDENTIAL
22
Count value
FFFFFFFFh
00000000h
input
7FFFFFFFh
0
A
B
Full count
Full count
E
※do not measurement by first edge
A
B
C
D
E
C(max value)
D(max value)
0
B+C(max value)
↓~↓
H
L
↓~↓
Interrupt factor
(cycle measurement by
↓edge)
interrupt
↑
Interrupt clear
Interrupt clear
↓~↓
C(max value)+D(max
value)
H
L
H
Cycle measurement
data register 0/1
data register 0/1
Over flow detect
Pulse width
measurement flag bit
0/1
measurement flag bit
0/1
Cycle measurement
flag bit 0/1
flag bit 0/1
Pulse width
measurement overflow
flag bit 0/1
measurement overflow
flag bit 0/1
Cycle measurement
overflow flag bit 0/1
overflow flag bit 0/1
Input capture data
register 0/1
register 0/1
Figure 5-5 Example of the Cycle and Pulse Width Measurement Operation (The falling edge is
specified).
When the falling edge is specified, cycle of from falling edge to falling edge is measured.
At this time, interrupt is not output though pulse width of from rising edge to falling edge and
from falling edge to rising edge is stored in input capture data register (IPCPn).
Input capture
data register 4/5
data register 4/5
Cycle measurement
data register 4/5
data register 4/5
Over flow detect
Pulse width measurement
over flow flag bit 4/5
over flow flag bit 4/5
Cycle measurement
over flow flag bit 4/5
over flow flag bit 4/5
Pulse width measurement
flag bit 4/5
Cycle measurement
flag bit 4/5
flag bit 4/5
Cycle measurement
flag bit 4/5
MB91520 Series
MN705-00010-1v0-E
897