Fujitsu FR81S User Manual
CHAPTER 24: 16-BIT FREE-RUN TIMER
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : 16-BIT FREE-RUN TIMER
FUJITSU SEMICONDUCTOR CONFIDENTIAL
18
[bit29] IRQZE: 0 detection interrupt request enable bit
IRQZE
Function
0
Interrupt request disabled
1
Interrupt request enabled
⋅
When this bit and interrupt flag bit (IRQZF: bit30) are set to "1", an interrupt request for CPU will be
generated.
[bit28 to bit26] MSI2 to MSI0: Interrupt mask selection bits
MSI2
MSI1
MSI0
Function
0
0
0
An interrupt will be generated when there is a match for the first time
0
0
1
An interrupt will be generated when there is a match for the second time
0
1
0
An interrupt will be generated when there is a match for the third time
0
1
1
An interrupt will be generated when there is a match for the fourth time
1
0
0
An interrupt will be generated when there is a match for the fifth time
1
0
1
An interrupt will be generated when there is a match for the sixth time
1
1
0
An interrupt will be generated when there is a match for the seventh time
1
1
1
An interrupt will be generated when there is a match for the eighth time
⋅
When MODE2: bit11 of the timer state control register (TCCS) is 0:
- These bits are used for configuring the mask count of compare clear interrupt in the up count mode
(MODE: bit21 of the timer state control register (TCCS) is 0). In the up/down count mode (MODE:
bit21 of the timer state control register (TCCS) is 1), they are used to configure the mask count of 0
detection interrupt.
- When this bit is set to "0", the interrupt factor will not be masked.
⋅
When MODE2: bit11 of the timer state control register (TCCS) is 1:
- In the up/down count mode (MODE: bit21 of the timer state control register (TCCS) is 1), these bits
are used to configure the mask count of 0 detection interrupt.
- Settings of the up count mode (MODE: bit21 of the timer state control register (TCCS) is 0) are
disabled.
Notes:
The value read is a mask counter value.
If a read-modify-write instruction is executed, the value read is a mask register value.
The written data will be written to the mask register.
The written value to the mask register while the free-run timer is active (STOP: bit22 of the timer state control
register (TCCS) is 0) will be reloaded to the counter only when the mask counter becomes "0".
The written value to the mask register while the free-run timer is inactive (STOP: bit22 of the timer state
control register (TCCS) is 1) will be immediately reloaded to the counter.
MB91520 Series
MN705-00010-1v0-E
925