Fujitsu FR81S User Manual
CHAPTER 24: 16-BIT FREE-RUN TIMER
5. Operation
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : 16-BIT FREE-RUN TIMER
FUJITSU SEMICONDUCTOR CONFIDENTIAL
38
5.2. Operation of the 16-bit Free-run Timer
Operation of the 16-bit free-run timer are explained.
The 16-bit free-run timer starts counting up from the value configured at the timer data register (TCDT) after
reset. The count value will be used as base time of the 16-bit output compare and 16-bit input capture.
5.2.1.
Timer Clear
The count value of the 16-bit free-run timer will be cleared in any of the followings:
⋅
When there is a match with the compare clear register by the up count mode (MODE:bit21 of TCCS
register is 0).
⋅
When "1" is written to SCLR: bit20 of the TCCS register while it is active.
⋅
When "0000
H
" is written to the TCDT register while it is inactive.
⋅
When it has been reset.
The counter will be cleared as soon as it has been reset. In the case of a software clear or when there is a match
with the compare clear register, the counter will be cleared synchronously with the count timing.
Note:
Even when "1" is written to the SCLR: bit20 of the TCCS register while it is inactive, the count value of the
16-bit free-run timer will not be cleared.
If "0000
H
" is written in TCDT register during the up/down counter mode (MODE:bit21=1 of timer state
control register (TCCS)), an unintended counting may be performed.
See Section "4.2.2. Timer Data Register (TCDT0 to TCDT2)" for the setting procedure of TCDT register
during the up/down counter mode (MODE:bit21=1 of timer state control register (TCCS)).
Figure 5-1 Clear Timing of the 16-bit Free-run Timer
Peripheral clock
Compare clear
Compare clear
register value
N
Compare match
N
0000
H
Count value
MB91520 Series
MN705-00010-1v0-E
945