Fujitsu FR81S User Manual
CHAPTER 24: 16-BIT FREE-RUN TIMER
5. Operation
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : 16-BIT FREE-RUN TIMER
FUJITSU SEMICONDUCTOR CONFIDENTIAL
43
5.2.5.
Interrupt Mask Function
You can mask either or both of the 0 detection interrupt and compare match interrupt. The following
explains how to mask either one of the interrupts.
⋅
You will be able to mask the interrupt request by setting the MSI2 to MSI0: bit28 to bit26 of the TCCS
register. MSI2 to MSI0 bits are 3-bit reload down register that reloads the value once the count value
reaches "000
B
". You can also load the count value by writing the value to the MSI2 to MSI0 bits
directly. Mask count is the value configured at MSI2 to MSI0. When the MSI2 to MSI0 bits become
"000
B
", the interrupt request will not be masked.
⋅
The interrupt request varies depending on the count mode (MODE: bit21 of the TCCS register). In the
up count mode, you will be able to mask the compare clear interrupts only while the 0 detection
interrupts will be generated every time "0" is detected. In the up/down count mode, you will be able to
mask the 0 detection interrupts only.
The following explains how to mask both types of interrupt requests.
⋅
Only when the free-run timer is in the up/down count mode, you will be able to mask both types of
interrupts by setting MODE2 of the TCCS register to 1 and MODE of the TCCS register to 1.
MSI2 to MSI0 bits of the TCCS register are used for masking the 0 detection interrupts and MSI5 to MSI3
bits of the TCCS register are used for masking the compare clear interrupts.
Note:
Software clear (SCLR: bit20 of the TCCS register is 1) does not generate the 0 detection interrupt.
Figure 5-8 Compare Clear Interrupt Masked in the Up Count Mode
FFFF
H
BFFF
H
7FFF
H
3FFF
H
0000
H
Count value
Time
0 detection interrupt
Compare clear interrupt
Timer operation start
First
time
Second
time
Third
time
Fourth
time
Fifth
time
Sixth
time
Seventh
time
Eighth
time
Ninth
time
TCCS.MSI2-MSI0=000
B
TCCS.MSI2-MSI0=001
B
TCCS.MSI2-MSI0=010
B
Note: Both 0 detection interrupts and compare clear interrupts are cleared by software.
MB91520 Series
MN705-00010-1v0-E
950