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ARM720T
User Manual
Epson ARM720T User Manual
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CONTENTS
ARM720T CORE CPU MANUAL EPSON vii
Table 9-7
Determining the cause of entry to debug state ......................................... 9-32
Table 9-8
SIZE[1:0] signal encoding ......................................................................... 9-35
Table 9-9
Debug control register bit assignments..................................................... 9-39
Table 9-10
Interrupt signal control............................................................................... 9-40
Table 9-11
Debug status register bit assignments ...................................................... 9-41
Table 10-1
Connections between the ETM7 macrocell and
the ARM720T processor ........................................................................... 10-2
Table 11-1
Summary of ATPG test signals ................................................................. 11-2
Table 11-2
Test State Register operations.................................................................. 11-3
Table 11-3
Summary of CP15 register c7, c9, and c15 operations............................. 11-4
Table 11-4
Write cache victim and lockdown operations ............................................ 11-6
Table 11-5
CAM, RAM1, and RAM2 register c15 operations...................................... 11-9
Table 11-6
Register c2, c3, c5, c6, c8, c10, and c15 operations ................................ 11-9
Table 11-7
CAM memory region size........................................................................ 11-10
Table 11-8
Access permission bit setting.................................................................. 11-11
Table 11-9
Miss and fault encoding .......................................................................... 11-11
Table 11-10
RAM2 memory region size...................................................................... 11-12
Table A-1
AMBA interface signals ...............................................................................A-1
Table A-2
Coprocessor interface signal descriptions ..................................................A-2
Table A-3
JTAG and test signal descriptions...............................................................A-3
Table A-4
Debugger signal descriptions......................................................................A-4
Table A-5
ETM interface signal descriptions ...............................................................A-5
Table A-6
ATPG test signal descriptions ....................................................................A-7
Table A-7
Miscellaneous signal descriptions...............................................................A-7
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