Epson ARM720T User Manual

This chapter describes the coprocessor interface on the ARM720T processor. It contains the 

following sections:

The instruction set for the ARM720T processor enables you to implement specialized 

additional instructions using coprocessors. These are separate processing units that are 

tightly coupled to the ARM720T processor. A typical coprocessor contains:

•

an instruction pipeline

•

instruction decoding logic

•

handshake logic

•

a  register  bank

•

special processing logic, with its own data path.

A coprocessor is connected to the same data bus as the ARM720T processor in the system, and 

tracks the pipeline in the ARM720T core. This means that the coprocessor can decode the 

instructions in the instruction stream, and execute those that it supports. Each instruction 

progresses down both the ARM720T processor pipeline and the coprocessor pipeline at the 

same time. 
The execution of instructions is shared between the ARM720T core and the coprocessor, as 

follows: 

The ARM720T core

1

Evaluates the condition codes to determine whether the 

instruction must be executed by the coprocessor, then signals 

this to any coprocessors in the system (using CPnCPI).

2

Generates any addresses that are required by the instruction, 

including prefetching the next instruction to refill the 

pipeline.

3

Takes the undefined instruction trap if no coprocessor accepts 

the instruction.