Epson ARM720T User Manual

Every coprocessor in the system must contain a pipeline follower to track the instructions 

executing in the ARM720T processor pipeline. The coprocessors connect to the ARM720T 

processor input data bus, EXTCPDOUT[31:0], over which instructions are fetched, and to 

HCLK and EXTCPCLKEN.
It is essential that the two pipelines remain in step at all times. When designing a pipeline 

follower for a coprocessor, you must observe the following rules:

•

At  reset  (HRESETn LOW), the pipeline must either be marked as invalid, or filled 

with instructions that do not decode to valid instructions for that coprocessor.

•

The coprocessor state must only change when EXTCPCLKEN is HIGH (except for 

reset).

•

An instruction must be loaded into the pipeline on the rising edge of HCLK, and 

only when CPnOPC, CPnMREQ, and CPTBIT were 

all

 LOW in the previous bus 

cycle.
These conditions indicate that this cycle is an ARM state opcode Fetch, so the new 

opcode must be sampled into the pipeline.

•

The pipeline must be advanced on the rising edge of HCLK when CPnOPC, 

CPnMREQ, and CPTBIT are all LOW in the current bus cycle.
These conditions indicate that the current instruction is about to complete 

execution, because the first action of any instruction performing an instruction 

fetch is to refill the pipeline.

Any instructions that are flushed from the ARM720T processor pipeline never signal on 

CPnCPI that they have entered Execute, so they are automatically flushed from the 

coprocessor pipeline by the prefetches required to refill the pipeline.
There are no coprocessor instructions in the Thumb instruction set, so coprocessors must 

monitor the state of the CPTBIT signal to ensure that they do not try to decode pairs of Thumb 

instructions as ARM instructions.