Epson ARM720T User Manual

Messages can be sent and received through the DCC.

Messages are sent from the processor to the debugger as follows:

1

When the processor wishes to send a message to EmbeddedICE-RT, it first checks 

that the communications data write register is free for use. The processor does this 

by reading the Domain Access Control Register to check the status of the W bit:
a.

If the W bit is clear, the DCC data write register is empty and a message is 

written by a register transfer to the coprocessor.

b.

If the W bit is set, this implies that previously-written data has not been read 

by the debugger. The processor must repeatedly read the Domain Access 

Control Register until the W bit is clear.

2

When the W bit is clear, a message is written by a register transfer to coprocessor 

14. The data transfer occurs from the processor to the DCC data write register, so 

the W bit is set in the Domain Access Control Register. 

3

When the debugger reads the Domain Access Control Register through the JTAG 

interface, it sees a synchronized version of both the R and W bits:
a.

When the debugger sees that the W bit is set, it can read the communications 

data write register and scan the data out. 

b.

The action of reading this data register clears the W bit of the Domain Access 

Control Register. At this point, the communications process can begin again.

Transferring a message from the debugger to the processor is similar to sending a message 

from the processor to the debugger. In this case, the debugger reads the R bit of the debug 

comms control register.
The sequence for receiving messages from the debugger is as follows:

1

The debugger reads the R bit of the Domain Access Control Register:
a.

If the R bit is clear, the data read register is free, and data can be placed there 

for the processor to read. 

b.

If the R bit is set, previously-deposited data has not yet been collected, so the 

debugger must wait.

2

When the communications data read register is free, data is written there using the 

JTAG interface. The action of this write sets the R bit in the Domain Access Control 

Register.

3

The processor reads the Domain Access Control Register:
a.

If the R bit is set, there is data that can be read using an MRC instruction to 

coprocessor 14. The action of this load clears the R bit in the debug comms 

control register. 

b.

If the R bit is clear, this indicates that the data has been taken and the process 

can now be repeated.