Epson ARM720T User Manual

The Debug Control Register is six bits wide. Writes to the Debug Control Register occur when 

a watchpoint unit register is written. Reads of the Debug Control Register occur when a 

watchpoint unit register is read. See 

information.
Figure 9-15 shows the function of each bit in the Debug Control Register.

Figure 9-15  Debug control register format

The Debug Control Register bit assignments are shown in Table 9-9.

Table 9-9  Debug control register bit assignments 

5

Used to disable the EmbeddedICE-RT comparator outputs while 
the watchpoint and breakpoint registers are being programmed. 
This bit can be read and written through JTAG.
Set bit 5 when:

•

programming breakpoint or watchpoint registers

•

changing bit 4 of the Debug Control Register.

You must clear bit 5 after you have made the changes, to 
re-enable the EmbeddedICE-RT logic and make the new 
breakpoints and watchpoints operational.

4

Used to determine the behavior of the core when breakpoints or 
watchpoints are reached:

•

If clear, the core enters debug state when a breakpoint 
or watchpoint is reached.

•

If set, the core performs an abort exception when a 
breakpoint or watchpoint is reached.

This bit can be read and written from JTAG.

3

This bit must be clear.

2

Used to disable interrupts:

•

If set, the interrupt enable signal of the core (IFEN) is 
forced LOW. The IFEN signal is driven as shown in 
Table 9-10.

•

If clear, interrupts are enabled.

1

Used to force the value on DBGRQ.

0

Used to force the value on DBGACK.

2

1

0

EmbeddedICE-RT

disable

Monitor mode

enable

SBZ/RAZ

5

4

3