Epson ARM720T User Manual

The functional signals on the ARM720T processor are shown in Figure 1-2.

Figure 1-2  ARM720T processor functional signals

The EmbeddedICE-RT logic provides integrated on-chip debug support for the ARM720T core. 

It enables you to program the conditions under which a breakpoint or watchpoint can occur.
The EmbeddedICE-RT logic is an enhanced implementation of EmbeddedICE, and enables 

you to perform debugging in monitor mode. In monitor mode, the core takes an exception on a 

breakpoint or watchpoint, rather than entering debug state as it does in halt mode.
If the core does not enter debug state when it encounters a watchpoint or breakpoint, it can 

continue to service hardware interrupt requests as normal. Debugging in monitor mode is 

useful if the core forms part of the feedback loop of a mechanical system, where stopping the 

core can potentially lead to system failure.
The EmbeddedICE-RT logic contains a 

Debug Communications Channel

 (DCC). The DCC is 

used to pass information between the target and the host debugger. The EmbeddedICE-RT 

logic is controlled through the 

Joint Test Action Group

 (JTAG) test access port.

A RM720T processor

A MBA

interf ace

Coprocessor

interf ace

Debug

interf ace

Miscellaneous

signals

A TPG

Signals

JTA G
interf ace

ETM interf ace

A TPG
Signals