Epson ARM720T User Manual

The ARM720T processor contains a CPSR, and five SPSRs for use by exception handlers. 

These registers:

•

hold information about the most recently performed ALU operation

•

control the enabling and disabling of interrupts

•

set the processor operating mode.

The arrangement of bits is shown in Figure 2-6.

Figure 2-6  Program status register format

The N, Z, C, and V bits are the condition code flags. These can be changed as a result of 

arithmetic and logical operations, and tested to determine if an instruction must execute or 

not.
In ARM state, all instructions can be executed conditionally. In Thumb state, only the Branch 

instruction is capable of conditional execution. See the 

ARM Architecture Reference Manual

 

for details.

The bottom eight bits of a PSR (incorporating I, F, T, and M[4:0]) are known collectively as the 

control bits. These change when an exception arises. If the processor is operating in a 

privileged mode, they can also be manipulated by software:

I and F bits 

These are the interrupt disable bits. When set, these disable the 

IRQ and FIQ interrupts respectively.

The T bit 

This reflects the operating state. When this bit is set, the processor 

is executing in Thumb state, otherwise it is executing in ARM 

state. This is reflected on the CPTBIT external signal. Software 

must never change the state of the CPTBIT in the CPSR. If this 

happens, the processor enters an Unpredictable state.

M[4:0] bits 

These are the mode bits. These determine the processor operating 

mode, as shown in Table 2-2 on page 2-9. Not all combinations of 

the mode bits define a valid processor mode. Only those explicitly 

described can be used. 

If you program any illegal value into the mode bits, M[4:0], then the processor 

enters an unrecoverable state. If this occurs, apply reset.

Condition

code flags

Control bits

Overflow (V)

Carry or borrow or extend (C)

Zero (Z)

Negative or less than (N)

31 30 29 28 27

8

6 5

0

IRQ disable (I)

Mode bits (M[4:0])

Reserved

2

3

State bit (T)

FIQ disable (F)

1

4

7