Epson ARM720T User Manual

The signals in the ARM720T processor bus interface can be grouped into the following 

categories:

Transfer type 

HTRANS[1:0]
See 

Address and control 

HADDR[31:0]
HWRITE
HSIZE[2:0]
HBURST[2:0]
HPROT[3:0]
See 

Slave transfer response 

HREADY
HRESP[1:0]
See 

 on page 6-9.

Data 

HRDATA[31:0]
HWDATA[31:0]
See 

Arbitration 

HBUSREQ
HGRANT
HLOCK
See 

Clock 

HCLK
HCLKEN
See 

Reset 

HRESETn
See 

Each of these signal groups shares a common timing relationship to the bus interface cycle. 

All signals in the ARM720T processor bus interface are generated from or sampled by the 

rising edge of HCLK.