AMD LX 600@0.7W User Manual
158
AMD Geode™ LX Processors Data Book
CPU Core Register Descriptions
33234H
5.5.2.61 Instruction Memory Subsystem BIST Tag MSR (IM_BIST_TAG_MSR)
The Instruction Memory subsystem supports built-in self-test (BIST) for the tag and data arrays. Normally, BIST is run dur-
ing manufacturing test. For convenience, BIST can be activated by reading the BIST MSRs.
ing manufacturing test. For convenience, BIST can be activated by reading the BIST MSRs.
WARNING: It is important that the instruction cache be disabled before initiating BIST via MSRs. There are no guarantees
of proper behavior if BIST is activated with the instruction cache enabled. The instruction cache can be disabled through
the IM_CONFIG_MSR (MSR 00001700h[4]).
of proper behavior if BIST is activated with the instruction cache enabled. The instruction cache can be disabled through
the IM_CONFIG_MSR (MSR 00001700h[4]).
5.5.2.62 Instruction Memory Subsystem BIST Data MSR (IM_BIST_DATA_MSR)
MSR Address
00001730h
Type
RO
Reset Value
00000000_0000000xh
IM_BIST_TAG_MSR Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RSVD
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
RSVD
CM
P
TA
G
IM_BIST_TAG_MSR Bit Descriptions
Bits
Name
Description
63:2
RSVD (RO)
Reserved (Read Only). (Default = 0)
1
CMP
Tag Compare Logic BIST.
0: Fail (Default)
1: Pass
1: Pass
0
TAG
Valid and Tag Array BIST.
0: Fail (Default)
1: Pass
1: Pass
MSR Address
00001731h
Type
RO
Reset Value
00000000_0000000xh
IM_BIST_DATA_MSR Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RSVD
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
RSVD
DA
T
A
IM_BIST_DATA_MSR Bit Descriptions
Bits
Name
Description
63:1
RSVD (RO)
Reserved (Read Only). (Default = 0)
0
DATA
Data Array BIST.
0: Fail
1: Pass
1: Pass