AMD LX 600@0.7W User Manual
342
AMD Geode™ LX Processors Data Book
Display Controller Register Descriptions
33234H
6.6.10.2 DC IRQ/Filter Control (DC_IRQ_FILT_CTL)
DC Memory Offset 094h
Type
DC Memory Offset 094h
Type
R/W
Reset Value
00000000h
DC_IRQ_FILT_CTL Register Map
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
RS
V
D
LINEB
U
F_SEL
INTE
R
L
A
C
E_ADDRESSING
RS
V
D
LINE_COUNT
RS
V
D
ALPHA_FIL
T
_ENA
RS
V
D
FIL
T
_ENA
IN
TL_EN
H_FIL
T
_SEL
RSVD
FILT_ADDR
DC_IRQ_FILT_CTL Bit Descriptions
Bit
Name
Description
31
RSVD
Reserved.
30:29
LINEBUF_SEL
Line Buffer Select. When LINEBUF_REG_EN[0] is set (bit 9 = 1), the coefficient RAM
address bits (FILT_ADDR, bits [7:0) and the Filter Coefficient Data registers (DC Memory
Offset 098h and 09Ch) can be used to read and write the line buffer or flicker filter RAMs.
This field selects which of the three line buffer RAMS (or two flicker filter RAMs) is to be
accessed.
address bits (FILT_ADDR, bits [7:0) and the Filter Coefficient Data registers (DC Memory
Offset 098h and 09Ch) can be used to read and write the line buffer or flicker filter RAMs.
This field selects which of the three line buffer RAMS (or two flicker filter RAMs) is to be
accessed.
28
INTERLACE_
ADDRESSING
ADDRESSING
Interlace Addressing. This bit indicates whether each field should be vertically deci-
mated when interlacing. If this bit is set, each field of the interlaced frame will include
every other line of the original (unscaled) frame buffer image. The flicker filter and scaler
filter should both be disabled if this bit is set.
mated when interlacing. If this bit is set, each field of the interlaced frame will include
every other line of the original (unscaled) frame buffer image. The flicker filter and scaler
filter should both be disabled if this bit is set.
27
RSVD
Reserved.
26:16
LINE_COUNT
Interrupt Line Count. This value determines which scan line will trigger a line count
interrupt. When the DC’s display engine reaches the line number determined by this
value, it will assert an interrupt if IRQ_MASK is cleared (DC Memory Offset 0C8h[0] = 0).
interrupt. When the DC’s display engine reaches the line number determined by this
value, it will assert an interrupt if IRQ_MASK is cleared (DC Memory Offset 0C8h[0] = 0).
15
RSVD
Reserved.
14
ALPHA_FILT_
ENA
ENA
Alpha Filter Enable. Settings written to this field will not take effect until the start of the
following frame or interlaced field.
following frame or interlaced field.
Setting this bit to 1 enables the scaler filter for the alpha channel. This filter is provided to
support scaling and interlacing of graphics data. If the graphics filter is disabled or this bit
is cleared, the alpha channel is not filtered; a nearest-neighbor mechanism is used
instead. This can provide cleaner transitions between regions with significantly different
alpha values.
support scaling and interlacing of graphics data. If the graphics filter is disabled or this bit
is cleared, the alpha channel is not filtered; a nearest-neighbor mechanism is used
instead. This can provide cleaner transitions between regions with significantly different
alpha values.
13
RSVD
Reserved.
12
FILT_ENA
Graphics Filter Enable. Settings written to this field will not take effect until the start of
the following frame or interlaced field.
the following frame or interlaced field.
Setting this bit to 1 enables the graphics scaler filter; This filter is provided to support
scaling and interlacing of graphics data.
scaling and interlacing of graphics data.