AMD LX 900@1.5W User Manual
AMD Geode™ LX Processors Data Book
383
Display Controller Register Descriptions
33234H
6.6.22.1 Video DAC Palette Address
6.6.22.2 Video DAC State
6.6.22.3 Video DAC Palette Data
Read Address
3C8h
Write Address
3C7h (Palette Read Mode)
3C8h (Palette Write Mode)
3C8h (Palette Write Mode)
Type
RO
Reset Value
00h
Video DAC Palette Address Register Bit Descriptions
Bit
Name
Description
7:0
ADDR
Palette Address.
Read Address
3C7h
Write Address
--
Type
RO
Reset Value
00h
Video DAC State Register Bit Descriptions
Bit
Name
Description
7:2
RSVD
Reserved.
1:0
DAC_ST
DAC State. This register returns the DAC state for save/restore operations. If the last
palette address write was to 3C7h (read mode), both bits are 1 (value = 11). If the last
palette address write was to 3C8h (write mode), both bits are 0 (value = 00).
palette address write was to 3C7h (read mode), both bits are 1 (value = 11). If the last
palette address write was to 3C8h (write mode), both bits are 0 (value = 00).
Read Address
3C9h
Write Address
3C9h
Type
R/W
Reset Value
00h
Video DAC Palette Data Register Bit Descriptions
Bit
Name
Description
7:6
RSVD
Reserved.
5:0
CO_CPN_VAL
Color Component Value. This is a 6-bit color component value that drives the video
DAC for the appropriate color component when the current palette write address is used
to address the video DAC in the pixel stream.
DAC for the appropriate color component when the current palette write address is used
to address the video DAC in the pixel stream.